GuideVLSI DesignVLSI Testing and Verification

VLSI Testing and Verification

A comprehensive guide to VLSI testing and verification techniques, including simulation-based verification, formal verification, physical testing, and built-in self-test (BIST) for embedded systems.

VLSI Testing and Verification

Testing and verification are critical aspects of VLSI design that ensure the correctness, reliability, and manufacturability of integrated circuits. This guide covers various testing and verification techniques used in modern VLSI design for embedded systems.

Simulation-Based Verification

Simulation-based verification uses software models to predict the behavior of a design under various conditions.

Here's an example of a simple testbench in SystemVerilog:

module counter_tb;
  // Clock period definition
  localparam CLK_PERIOD = 10;
  
  // Signals
  logic clk;
  logic reset;
  logic [7:0] count;
  
  // Instantiate the design under test
  counter dut (
    .clk(clk),
    .reset(reset),
    .count(count)
  );
  
  // Clock generation
  initial begin
    clk = 0;
    forever #(CLK_PERIOD/2) clk = ~clk;
  end
  
  // Test stimulus
  initial begin
    // Initialize
    reset = 1;
    #(CLK_PERIOD * 2);
    
    // Release reset
    reset = 0;
    
    // Wait for 10 clock cycles
    repeat(10) @(posedge clk);
    
    // Check count value
    if (count !== 8'd10)
      $error("Count mismatch: expected 10, got %d", count);
    else
      $display("Test passed: count = %d", count);
    
    // End simulation
    #(CLK_PERIOD * 2);
    $finish;
  end
  
  // Monitor changes
  initial begin
    $monitor("Time=%0t reset=%b count=%d", $time, reset, count);
  end
endmodule

Formal Verification

Formal verification uses mathematical methods to prove the correctness of a design.

Common formal verification methods include:

  • Model Checking: Exhaustively checking all possible states
  • Theorem Proving: Using mathematical proofs to verify properties
  • Equivalence Checking: Verifying that two designs are functionally equivalent
  • Property Checking: Verifying specific properties of a design

Formal methods can provide complete verification for certain properties.

Example of a SystemVerilog assertion:

// Property: Reset should clear the counter
property reset_clears_counter;
  @(posedge clk) reset |-> ##1 count == 0;
endproperty
 
// Assert the property
assert property (reset_clears_counter)
  else $error("Reset did not clear the counter");

Physical Testing

Physical testing involves applying test patterns to fabricated chips to detect manufacturing defects.

Test Pattern Generation

# Using ATPG tools to generate test patterns
tetramax -tcl -do "read_verilog design.v; run_atpg; write_patterns patterns.v"

Test Application

# Apply test patterns to the chip
test_runner -patterns patterns.v -device chip_id

Response Analysis

# Analyze test responses
analyze_responses -responses responses.log -expected expected.log

Built-In Self-Test (BIST)

BIST incorporates test circuitry directly into the chip to enable self-testing.

Common BIST types include:

  • Logic BIST (LBIST): Testing random logic
  • Memory BIST (MBIST): Testing embedded memories
  • Analog BIST: Testing analog circuits
  • Delay BIST: Testing timing-related defects

BIST can significantly reduce test time and improve test coverage.

Example of a simple BIST controller in Verilog:

module bist_controller(
    input  clk,
    input  reset,
    input  start,
    output reg test_mode,
    output reg pattern_gen_en,
    output reg response_comp_en,
    output reg done
);
    // State encoding
    localparam IDLE     = 2'b00;
    localparam TEST     = 2'b01;
    localparam COMPLETE = 2'b10;
    
    // State register
    reg [1:0] state, next_state;
    
    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= IDLE;
        else
            state <= next_state;
    end
    
    // Next state logic
    always @(*) begin
        case (state)
            IDLE: next_state = start ? TEST : IDLE;
            TEST: next_state = done ? COMPLETE : TEST;
            COMPLETE: next_state = IDLE;
            default: next_state = IDLE;
        endcase
    end
    
    // Output logic
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            test_mode <= 1'b0;
            pattern_gen_en <= 1'b0;
            response_comp_en <= 1'b0;
            done <= 1'b0;
        end else begin
            case (state)
                IDLE: begin
                    test_mode <= 1'b0;
                    pattern_gen_en <= 1'b0;
                    response_comp_en <= 1'b0;
                    done <= 1'b0;
                end
                TEST: begin
                    test_mode <= 1'b1;
                    pattern_gen_en <= 1'b1;
                    response_comp_en <= 1'b1;
                    done <= 1'b0;
                end
                COMPLETE: begin
                    test_mode <= 1'b0;
                    pattern_gen_en <= 1'b0;
                    response_comp_en <= 1'b0;
                    done <= 1'b1;
                end
                default: begin
                    test_mode <= 1'b0;
                    pattern_gen_en <= 1'b0;
                    response_comp_en <= 1'b0;
                    done <= 1'b0;
                end
            endcase
        end
    end
endmodule

Fault Models and Testing

Fault models represent the types of defects that can occur during manufacturing.

Test Pattern Generation

Test pattern generation creates patterns that detect manufacturing defects.

Automatic Test Pattern Generation (ATPG) techniques include:

  • D-Algorithm: Classic ATPG algorithm
  • PODEM: Path-Oriented Decision Making
  • FAN: Fanout-Oriented Test Generation
  • SAT-Based ATPG: Using Boolean satisfiability

ATPG tools generate patterns to detect specific fault models.

Next Steps

Now that you understand VLSI testing and verification, you can explore:

VLSI Design TechniquesVLSI Applications